1. Field of the Present Invention
The present invention generally relates to the filed of microprocessors and more particularly to a dual core microprocessor implemented with one or more shared execution units.
2. History of Related Art
Increased microprocessor performance is sometimes achieved by simply increasing the number of resources, such as execution units in the microprocessors. Increasing the number of resources theoretically enables a corresponding increase in the maximum number of instructions that the processor can execute. While increased performance is highly desirable, the increase in performance achieved by any additional resources typically must be weighed against the cost required to achieve the increased performance in the form of increased device size. Larger devices are more expensive because (1) fewer devices can be fabricated per wafer and (2) the probability of a random defect rendering the device non-functional increases with the size of the device. Therefore, because of the significant cost considerations associated with each additional resource, it is highly desirable to add only those additional resources where the performance benefit achieved more than compensates for the increased cost. Conversely, it is desirable to share resources where the performance penalty resulting from the shared resource is more than offset by the reduction in size and cost.
A microprocessor, data processing system and a method of operation are disclosed. The processor includes a first processor core and a second processor core that are preferably fabricated on a single substrate. The first core includes a first instruction cache, a first data cache, and a first processing block. The first processing block is adapted to retrieve instructions from the first instruction cache and data from the first data cache. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second instruction cache, a second data cache, and a second processing block. The second processing block is adapted to retrieve instructions from the second instruction cache and data from the second data cache. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions. The processor may further include an arbiter an arbiter connected to the shared execution unit for arbitrating between the first processor core and the second processor core for access to the shared execution unit. In one embodiment, each processor core may include a shared execution enable bit that is utilized by the arbiter to control the status of the shared enable bit. In one embodiment the shared execution unit includes a pair of execution pipes. The shared execution unit may be connected to and receive instructions from a shared issue unit.